It is well known to provide a PLL using a VCRO for generating a local clock signal which is locked in frequency and phase to a reference frequency, and to use frequency dividers in such a PLL to provide a desired relationship between the frequency of the local clock signal and the reference frequency. In such an arrangement, the VCRO conveniently comprises an inverting delay line whose output is connected to its input, the delay line comprising a plurality of identical delay elements whose delay is determined by a control voltage which is supplied by the PLL to determine the oscillation frequency of the VCRO.
It is also known, from Bell et al. U.S. Pat. No. 4,494,021 issued Jan. 15, 1985 and entitled "Self-Calibrated Clock And Timing Signal Generator For MOS/VLSI Circuitry", to provide such an arrangement for calibrating a tapped delay line, comprising further identical delay elements controlled by the same control voltage, whose output taps are coupled to a programmable logic circuit to provide arbitrary output waveforms from an input signal supplied to the tapped delay line.
Tomisawa U.S. Pat. No. 4,988,960 issued Jan. 29, 1991 and entitled "FM Modulation Device And FM Demodulation Device Employing A CMOS Signal Delay Device" discloses another arrangement of a PLL using a VCRO including delay elements whose control voltage is also used to control the delay of identical delay elements in a controlled circuit, such as an FM modulator or demodulator.
These references are not concerned with phase error detection or with phase lock detection for the PLL.
An object of this invention is to provide an improved phase error detector for a PLL using a VCRO.